Jalapeño is 700 watts

Each chip carries 216 GB of HBM4 at up to 15.4 TB/s and 13.4 MXFP4 petaFLOPS. Sixty-four memory-and-core slices keep operands local. A rack-scale domain is 128 accelerators. A 2,048-processor system is the scale-up target OpenAI put on the board: 27 exaFLOPS of MXFP4 compute and 32 PB/s of aggregate memory bandwidth, tied together with Broadcom Tomahawk 6 Ethernet. LavX’s Hot Chips write-up of the same deck puts the 128-chip local domain over a petabyte a second of HBM bandwidth and the 2,048-chip global domain at 432 TiB of HBM. The 700-watt package is the constant that makes the rest of the arithmetic a night-desk story.

Tape-out in nine months is the industrial sentence OpenAI has used since it unveiled the part with Broadcom in June. Silicon is already in the lab. Codex has run on it. Celestica is on the boards and racks. The programming model is spatial: tensors placed on purpose, cores treated as thread blocks. SemiAnalysis, invited to look at the chip and run InferenceX, separately dated design work from mid-2024 hiring to manufacturing tape-out at about 16 months. Those are two clocks. One is OpenAI’s nine-month tape-out line. The other is a reporter’s hiring-to-fab span. Both stay on the page, attributed.

The Register’s 25 August report is the other date-stamped copy: trickle later this year, volume in 2027. That is not a launch-day in a shopping cart. It is a lab part with a calendar. Hot Chips is where a company that used to rent other people’s silicon stands up and names watts, HBM4 pin rate, and a rack of 128. Nvidia’s GB300, in the same comparison OpenAI asked for, is listed at 1,400 watts. GB200 at 1,200. AMD’s MI355X shows up in some of the same power-normalised tables at 1,400. Jalapeño’s argument is that inference does not have to live at those envelopes to serve the models OpenAI already runs.

Ho, Narayanaswami, and Leary are the named walkers of the nine-month tape. The architecture they described keeps memory next to the slice that will use it. That is the NUMA sentence without the brochure: 64 slices, each with a local HBM view, so the common operand does not have to tour the package. 13.4 MXFP4 petaFLOPS is the compute they put on one 700-watt lid. 15.4 TB/s is the HBM4 number that SemiAnalysis read as 10 Gbps pin speed, an early HBM4 adopter after Nvidia and AMD, not a TPU footnote.

A 128-accelerator rack is the local domain. OpenAI’s own slide math, as The Register reconstructed it, puts that rack at about 1.7 exaFLOPS of 4-bit compute, 27.5 TB of HBM4, and just shy of 2 PB/s of memory bandwidth. The 2,048-chip global domain is the bigger sentence: Tomahawk 6 for the Ethernet, two-level Clos in the LavX notes, 200 GB/s on the global side and 600 GB/s inside the local domain. The story is the watts. The network exists so 700 watts times 128 is still a system you can cool.

Codex on the lab silicon is the product proof OpenAI offered without a storefront. Celestica on the boards and racks is the contract manufacturer in the sentence. Broadcom is the partner that has been in the copy since June. TSMC N3P is the process SemiAnalysis named; OpenAI’s Hot Chips talk, as filed here, did not need that foundry line to make 700 watts true. If a later deck names N3P on the record, that name can be added. Today the record is the package, the HBM4, the three presenters, and the Stanford date.

InferenceX is SemiAnalysis’s suite. OpenAI used it in public, power-normalised, on GPT-OSS-120B, DeepSeek R1, and Kimi K2.5. Prefill and decode both sit in that comparison. The 1.5 to 1.9 times throughput-per-watt range and the 1.7 to 3.6 times latency range are the two claims that survive a night file. They are not a substitute for a customer rack in a colo. They are a Hot Chips claim with named models and named watts.

June was the unveil. August 25 was the first time the same part sat still for a semiconductor conference with watts, HBM4, and a rack count a night editor can file without a myth. Stanford is the place. Hot Chips is the week. Jalapeño is the name they were willing to print on the slide.

Night desks like a chip that argues in watts. Seven hundred is the argument. The rest is a factory story that has not yet shipped in volume: silicon in the lab, Codex already running, Celestica building the box, 2027 on the volume line, and a 700-watt lid that OpenAI was willing to put next to a 1,400-watt Nvidia number on a Tuesday at Stanford.
The 700-watt lid is also a cooling story. A night file does not need a thermal diagram. It needs a number you can put next to Nvidia’s 1,400 and still have room in a rack. OpenAI put that number on a Stanford slide on 25 August. Broadcom is in the byline of the silicon. Celestica is in the byline of the board. Codex is in the byline of the lab. Volume is 2027. The trickle is later this year. None of that changes the kicker: seven hundred watts, 216 GB of HBM4, 13.4 MXFP4 petaFLOPS, and three named engineers walking the tape at Hot Chips.

The next number is a customer shipment when a rack leaves a dock with a date on the truck. Tuesday was not that day. Tuesday was the day the watts were allowed to be the lead.